This article <https://www.sigarch.org/simd-instructions-considered-harmful/> (linked from <https://www.theregister.com/2020/10/21/sifive_vector_cpu_core/>) goes into how RISC-V implements vector instructions, and how this differs from the conventional SIMD approach taken by existing architectures like x86, ARM and MIPS. These CPUs add instructions that can operate on two, four or eight operands at once, in parallel. One drawback is that every new data type (and every new extension to dealing with greater parallelism) requires a new set of instructions, and so we a massive growth in the size of instruction sets for these machines over time. And then there is the trickiness of generating code using these instructions: even though you mostly leave it to the compiler to worry about this sort of thing nowadays, it still involves the generation of complicated sequences to set up a loop and deal with odd numbers of operands that don’t fit into the exact multiples that the instructions can deal with. So you wonder why a small sequence of source code can generate a whole lot of machine code. RISC-V, on the other hand, hearkens back to the grand-daddy of vector machines, the original Cray supercomputer family from the 1970s and 1980s. Here you have a vector-length register, which tells the CPU how many operands you have. You then set up operand pointer registers and write basically one instruction that operates on a single set of operands, and leave it to the hardware to automatically repeat this operation the required number of times, batching the iterations up to whatever size a particular implementation can handle in parallel. So the same code can run unchanged on future hardware with more parallel function units, and automatically take advantage of the greater performance.